1. Field of the Invention
The present invention relates in general to a method of forming a multilayer interconnection structure, and more particularly to a method of filling a through-hole with a conductive material by a chemical vapor deposition (CVD) method so as to obtain a multilayer interconnection.
2. Description of the Prior Art
A multilayer or three dimensional interconnection structure of a semiconductor device has been recently proposed to minimize the interconnection resistance and to save valuable chip area.
It is known to form a multilayer interconnection structure by a selective CVD method with using tungsten. This method comprises the following steps in the sequence.
First, a first insulating layer is deposited on a first conductive layer, followed by the deposition of a second conductive layer on the first insulating layer. Then, a second insulating layer is deposited on the second conductive layer, so as to form a multilayer structure. Then, a through-hole is formed on the multilayer structure so as to expose an upper surface of the first conductive layer. The first and second conductive layers are made of polycrystaline silicon (polysilicon), and the first and second insulating layers are made of SiO.sub.2. Then, a conductive material such as tungsten is deposited in the through-hole using a selective CVD method. It is noted that tungsten is selectively deposited on polysilicon surface by the CVD method, and not on SiO.sub.2 surface. Due to this characteristic of tungsten, it can be selectively deposited on the exposed upper surface of the first conductive layer and on two exposed side surfaces of the second conductive layer. If a through-hole has a relatively low aspect ratio, the through-hole will be filled with tungsten by growing tungsten deposition. However, due to a recent demand for high integration of semiconductor devices, the through-hole has a relatively high aspect ratio. Due to this, the through-hole tends to be blocked up by the growth of tungsten deposition on the side surfaces of the second conductive layer. With this, an undesirable void space is left in the through-hole. This space makes the first and second conductive layers unconnected with each other.
To prevent the formation of the void space, as is disclosed in Japanese Patent No. 4-373149, there is another conventional method of forming a multilayer interconnection structure. This method having the following steps in the sequence will be described with reference to FIGS. 8 and 9.
First, a multilayer structure 10 is formed by depositing on a first conductive layer (polysilicon film) 12 a first insulating layer (SiO.sub.2 film) 14, a second conductive layer (Si film) 16 and a second insulating layer (SiO.sub.2 film) 18 in turn. Then, a through-hole 20 is formed on the multilayer structure 10 so as to expose an upper surface of the first conductive layer 12 and side surfaces of the second conductive layer 16. Then, a SiO.sub.2 film 22 is deposited on an upper surface of the second insulating layer 18 and on the through-hole 20. After that, the deposited SiO.sub.2 film 22 was partially removed so as to leave only its side wall portion on the through-hole 20. Then, as is seen from FIG. 8, tungsten is selectively deposited by a CVD method on the upper surface of the first conductive layer 12 in a vertical direction until the top surface of the deposited tungsten 24 reaches a height just below that of a bottom surface of the second conductive layer 16. Then, upper portions of the side wall portions of the SiO.sub.2 film 22 are removed by isotropic etching so as to expose the side surfaces of the second conductive layer 16. Then, tungsten is selectively deposited by a CVD method on the side surfaces of the second conductive layer 16 so as to fill the through-hole with tungsten. However, as is seen from FIG. 9, the second conductive layer of Si film 16 is eroded by the reducing effect of the CVD method. This may lead the increase of junction leak of a transistor. Furthermore, electric contact resistance of Si or polysilicon relative to tungsten is higher than that relative to Al or Ti. In particular, as the thickness of the second conductive layer of Si film 16 becomes thinner, parasitic resistance of a transistor is increased when tungsten is used for interconnecting a multilayer structure.